VLSI academia

VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world into a better one

We have training on RTL design, Synthesis, DFT, Emulation, Integration, Timing and Power Signoff, STA, Physical Design, RTLtoGDSII and lot more

24*7 support with 1 on 1 doubt solving
High quality study material and interactive live sessions
Guidance for placement in VLSI Industry
Early Bird Offer : 20 % Off for first 100 students
100 % placement assistance
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Modports
Modports
UVM Phases
UVM Phases
Setup & Hold Analysis | Fix Setup and Hold Analysis
Setup & Hold Analysis | Fix Setup and Hold Analysis
Event Regions in Verilog and Race Condition
Event Regions in Verilog and Race Condition
Static timing Analysis in Design Flow
Static timing Analysis in Design Flow
SV Verification Constructs | Final Block | Fork Join | join_any | join none | disable and wait fork
SV Verification Constructs | Final Block | Fork Join | join_any | join none | disable and wait fork
Interfaces in System Verilog
Interfaces in System Verilog
Design gates (NOT/ OR/ AND/ XOR/ XNOR/ Full adder) using mux
Design gates (NOT/ OR/ AND/ XOR/ XNOR/ Full adder) using mux
Time literal and timescale in System Verilog | Timeunit | Timeprecision
Time literal and timescale in System Verilog | Timeunit | Timeprecision
User defined data type in System Verilog | Enumerated Data Types | typedef
User defined data type in System Verilog | Enumerated Data Types | typedef
What is Static timing analysis | Why it is important
What is Static timing analysis | Why it is important
Design gates (NOT/ OR / AND / XOR / XNOR/ Majority) using NAND gate
Design gates (NOT/ OR / AND / XOR / XNOR/ Majority) using NAND gate
Static vs Dynamic Timing Analysis | Basic of Static Timing Analysis
Static vs Dynamic Timing Analysis | Basic of Static Timing Analysis
Classes in System Verilog - Part II | SV for Verification and OOPs concept
Classes in System Verilog - Part II | SV for Verification and OOPs concept
Classes in System Verilog - Part I | SV for Verification and OOPs concept
Classes in System Verilog - Part I | SV for Verification and OOPs concept
Basics of classes - Introduction
Basics of classes - Introduction