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001 LAB Heart Bit 01 Introduction in vhdl verilog fpga
002 LAB Heart Bit 02 Simulation in vhdl verilog fpga
003 LAB Heart Bit 03 Layout and Test in vhdl verilog fpga
002 Bonus2 Test bench Write to File in vhdl verilog fpga
001 Bonus1 Test bench Read Form File in vhdl verilog fpga
001 Introduction to TextIO library in vhdl verilog fpga
001 29 Generate Statement in vhdl verilog fpga
004 24 Assert Statement
008 28 Packages
006 26 Wait Statement
001 21 Sequential Modeling in vhdl verilog fpga
005 25 Sensitivity List vs Wait Statement
002 22 Sequential Conditional Statement
003 23 Sequential Iteration Statement
007 27 Subprogram
001 01 Introduction to Modelsim in vhdl verilog fpga
002 02 Introduction to Modelsim in vhdl verilog fpga
002 15 Types of Data Object in vhdl verilog fpga
005 18 Signed Unsigned in vhdl verilog fpga
004 17 VHDL User defined data type in vhdl verilog fpga
003 16 bit vs ulogic vs std logic in vhdl verilog fpga
007 20 Subtype in vhdl verilog fpga
001 14 Predefined DataTypes in vhdl verilog fpga
006 19 Type Conversion and Casting in vhdl verilog fpga
008 13 Driver and Source in vhdl verilog fpga
004 09 VHDL Delay Modeling in vhdl verilog fpga
007 12 Generics in vhdl verilog fpga
