Telugu Engineering


For any business related queries contact

[email protected]

Parallel Block Statements - Example with Fork-Join || Verilog lectures in Telugu - 34
Parallel Block Statements - Example with Fork-Join || Verilog lectures in Telugu - 34
Initial Block Example || Verilog lectures in Telugu - 33
Initial Block Example || Verilog lectures in Telugu - 33
Initial Block || Verilog lectures in Telugu - 32
Initial Block || Verilog lectures in Telugu - 32
4-bit Left Shift Register - sequential design || Verilog lectures in Telugu - 31
4-bit Left Shift Register - sequential design || Verilog lectures in Telugu - 31
4:16 Decoder - sequential design || Verilog lectures in Telugu - 30
4:16 Decoder - sequential design || Verilog lectures in Telugu - 30
4:16 Decoder - combinational design || Verilog lectures in Telugu - 29
4:16 Decoder - combinational design || Verilog lectures in Telugu - 29
1:4 Demultiplexer - combinational design || Verilog lectures in Telugu - 27
1:4 Demultiplexer - combinational design || Verilog lectures in Telugu - 27
Combinational Design - Full Adder || Verilog lectures in Telugu - 27
Combinational Design - Full Adder || Verilog lectures in Telugu - 27
Combinational Design - Full Adder || Verilog lectures in Telugu - 25
Combinational Design - Full Adder || Verilog lectures in Telugu - 25
Combinational Design - Half Adder || Verilog lectures in Telugu - 25
Combinational Design - Half Adder || Verilog lectures in Telugu - 25
Always Block || Verilog lectures in Telugu - 23
Always Block || Verilog lectures in Telugu - 23
Designing combinational & Sequential design using always block ||
Designing combinational & Sequential design using always block ||
Concatenation & Replication Operators ||Verilog lectures in Telugu - 22
Concatenation & Replication Operators ||Verilog lectures in Telugu - 22
Operators || Verilog lectures in Telugu - 21
Operators || Verilog lectures in Telugu - 21
Assign statements || Verilog lectures in Telugu - 20
Assign statements || Verilog lectures in Telugu - 20
Module Instantiation - Methods || Verilog lectures in Telugu - 19
Module Instantiation - Methods || Verilog lectures in Telugu - 19
Ports & It's types || Verilog lectures in Telugu - 18
Ports & It's types || Verilog lectures in Telugu - 18
Module & It's purpose || Verilog lectures in Telugu - 17
Module & It's purpose || Verilog lectures in Telugu - 17
Memories in Verilog || Verilog lectures in Telugu - 16
Memories in Verilog || Verilog lectures in Telugu - 16
Arrays & Array assignment || Verilog lectures in Telugu - 15
Arrays & Array assignment || Verilog lectures in Telugu - 15
Bit-Select & Part-Select | Verilog lectures in Telugu - 14
Bit-Select & Part-Select | Verilog lectures in Telugu - 14
Scalar & Vector | Verilog lectures in Telugu - 13
Scalar & Vector | Verilog lectures in Telugu - 13
Examples for Data-Types || Verilog lectures in Telugu - 12
Examples for Data-Types || Verilog lectures in Telugu - 12
Integer, real, time, real time|| Verilog lectures in Telugu - 11
Integer, real, time, real time|| Verilog lectures in Telugu - 11
Identifiers & Keywords || Verilog lectures in Telugu - 7
Identifiers & Keywords || Verilog lectures in Telugu - 7
Wire | Datatypes || Verilog lectures in Telugu - 9
Wire | Datatypes || Verilog lectures in Telugu - 9
Nets | Datatypes || Verilog lectures in Telugu - 9
Nets | Datatypes || Verilog lectures in Telugu - 9
Content of the variable & It's significance || Verilog lectures in Telugu - 8
Content of the variable & It's significance || Verilog lectures in Telugu - 8
Operators and Number Format || Verilog lectures in Telugu - 6
Operators and Number Format || Verilog lectures in Telugu - 6
Comments & White spaces || Verilog lectures in Telugu - 5
Comments & White spaces || Verilog lectures in Telugu - 5