張哲文

I am Owen. This is the place i share my research about the combination of HDL Coder and Zynq, which i think will change the future of the system design.

LittleBits workshop 20151128
LittleBits workshop 20151128
Mathworks HDL Coder Sobel on Zynq Step by Step to build entire system and live demo
Mathworks HDL Coder Sobel on Zynq Step by Step to build entire system and live demo
Zedboard HDL Coder Sobel Filter Live Demo
Zedboard HDL Coder Sobel Filter Live Demo
ZC702 HDL Coder Sobel Filter Live Demo
ZC702 HDL Coder Sobel Filter Live Demo
Create IP (with DMA Master) to Access DDR via ACP Port
Create IP (with DMA Master) to Access DDR via ACP Port
HDL Coder 2.1 and Embedded Coder 2.2 Setup for Zynq with ISE 14.4
HDL Coder 2.1 and Embedded Coder 2.2 Setup for Zynq with ISE 14.4
7.SDK programming and debugging with ZC702 (HDL-Coder Add success!) [HDL coder + Zynq Project]
7.SDK programming and debugging with ZC702 (HDL-Coder Add success!) [HDL coder + Zynq Project]
6.Run Synthesis,Implementaion,Generate Bitstream,Export to SDK [HDL coder + Zynq Project]
6.Run Synthesis,Implementaion,Generate Bitstream,Export to SDK [HDL coder + Zynq Project]
5.Run IP status for IP upgrade (modified Out32 to Out8) [HDL coder + Zynq Project]
5.Run IP status for IP upgrade (modified Out32 to Out8) [HDL coder + Zynq Project]
4. Integrate HDL Coder-Add Block into IP catalog [HDL coder + Zynq Project]
4. Integrate HDL Coder-Add Block into IP catalog [HDL coder + Zynq Project]
3. Using Vivado IP Packager to create HDL Coder-Add Block [HDL coder + Zynq Project]
3. Using Vivado IP Packager to create HDL Coder-Add Block [HDL coder + Zynq Project]
2. Create simple
2. Create simple "Add" Block, and generate RTL by HDL Coder in Simulink [HDL coder + Zynq Project]
1.How to use Vivado 2013.3 IP Integrator for Zynq [HDL coder + Zynq Project]
1.How to use Vivado 2013.3 IP Integrator for Zynq [HDL coder + Zynq Project]
Export Simulink Design by HDL Coder
Export Simulink Design by HDL Coder