TheShivakesh

Happy Welcome.

2x1 Multiplexer Verilog Code | Simulate and explain in VS code #verilog #vscode
2x1 Multiplexer Verilog Code | Simulate and explain in VS code #verilog #vscode
Full Subtractor Using Verilog | Design and Simulation | GTKWave #verilog #vscode #digitaldesign
Full Subtractor Using Verilog | Design and Simulation | GTKWave #verilog #vscode #digitaldesign
Design a Full Adder in verilog using VS Code
Design a Full Adder in verilog using VS Code
Half Subtractor Using Verilog | Easy Simulation in VS Code & GTKWave.
Half Subtractor Using Verilog | Easy Simulation in VS Code & GTKWave.
Half Adder in Verilog | Testbench + GTKWave | Complete Simulation Tutorial #verilog #halfadder
Half Adder in Verilog | Testbench + GTKWave | Complete Simulation Tutorial #verilog #halfadder
Build a Synchronous Counter in Verilog | VS Code + GTKWave Output | #verilog #vscode #counter
Build a Synchronous Counter in Verilog | VS Code + GTKWave Output | #verilog #vscode #counter
Jai Bhavani Pooja #saraswatipuja #durgapuja #dussehra
Jai Bhavani Pooja #saraswatipuja #durgapuja #dussehra
JNTUH UNIVERSITY COLLEGE OF ENGINEERING RAJANNA SIRICILLA|| CAMPUS TOUR || LABS || PART -2||
JNTUH UNIVERSITY COLLEGE OF ENGINEERING RAJANNA SIRICILLA|| CAMPUS TOUR || LABS || PART -2||
JNTUH UNIVERSITY OF RAJANNA SIRICILLA 😍|| CAMPUS TOUR || PART -1
JNTUH UNIVERSITY OF RAJANNA SIRICILLA 😍|| CAMPUS TOUR || PART -1
Mahabarat skit ⭐|| Krishnaveni Talent School 2018-19 Batch|| SHIVAKESH
Mahabarat skit ⭐|| Krishnaveni Talent School 2018-19 Batch|| SHIVAKESH