husam ahmed

High-Level Synthesis with CyberWorkBench (DE1-SoC Lab Tutorial)
High-Level Synthesis with CyberWorkBench (DE1-SoC Lab Tutorial)
VGA Image generator
VGA Image generator
DE1 Soc VGA FPGA Interface
DE1 Soc VGA FPGA Interface
FPGA Physical Design and Timing DE1 SOC Quartus prime
FPGA Physical Design and Timing DE1 SOC Quartus prime
Prototyping LMP Multiplier IP on DE1 Soc 7 SGMENTS display
Prototyping LMP Multiplier IP on DE1 Soc 7 SGMENTS display
Prototyping LMP Multiplier IP on DE1 Soc
Prototyping LMP Multiplier IP on DE1 Soc
Prototyping on the Terasic DE1 SoC board 10 LEDs
Prototyping on the Terasic DE1 SoC board 10 LEDs
Prototyping on the Terasic DE1 SoC board
Prototyping on the Terasic DE1 SoC board
Building and simulating 1 bit full adder using Quartus Prime Design Suite
Building and simulating 1 bit full adder using Quartus Prime Design Suite