Yourmkj

How to Export Plots & CSV Files from Cadence Virtuoso to Your System | Step-by-Step Guide
How to Export Plots & CSV Files from Cadence Virtuoso to Your System | Step-by-Step Guide
Cadence Tutorial | Inverter Simulation: Propagation Delay & Noise Margin Analysis
Cadence Tutorial | Inverter Simulation: Propagation Delay & Noise Margin Analysis
Classical PLL Design at 180nm | Complete Walkthrough with GitHub & Word Report
Classical PLL Design at 180nm | Complete Walkthrough with GitHub & Word Report
"PLL Design on Cadence Virtuoso | Lecture: 5 Complete PLL Integration & Locking at 4.8 GHz”
“PLL Design on Cadence Virtuoso | Lecture 4: Asynchronous Divider (/48) using TSPC D Flip-Flops”
“PLL Design on Cadence Virtuoso | Lecture 4: Asynchronous Divider (/48) using TSPC D Flip-Flops”
“PLL Design on Cadence Virtuoso | Lecture 3.1: Current Starved VCO Symbol Creation”
“PLL Design on Cadence Virtuoso | Lecture 3.1: Current Starved VCO Symbol Creation”
“PLL Design on Cadence Virtuoso | Lecture 3: Current Starved VCO Design, Simulation & KVCO Analysis”
“PLL Design on Cadence Virtuoso | Lecture 3: Current Starved VCO Design, Simulation & KVCO Analysis”
Inverter Analysis in VLSI | Noise Margin, Power, Propagation Delay & PMOS Width Adjustment | MK Jha
Inverter Analysis in VLSI | Noise Margin, Power, Propagation Delay & PMOS Width Adjustment | MK Jha
“PLL Design on Cadence Virtuoso | Lecture 2: Charge Pump Schematic & Simulation”
“PLL Design on Cadence Virtuoso | Lecture 2: Charge Pump Schematic & Simulation”
“PLL Design on Cadence Virtuoso | Lecture 1: Phase Frequency Detector (PFD) Schematic & Simulation”
“PLL Design on Cadence Virtuoso | Lecture 1: Phase Frequency Detector (PFD) Schematic & Simulation”
"5-Stage Ring Oscillator Design & Simulation in Cadence Virtuoso | Full schematic|IIT Patna| MK JHA"
"5-Stage Ring Oscillator Simulation in Cadence Virtuoso | Frequency Analysis | IIT Patna | MK JHA"
"2-Input NOR & 2-Input OR Gate using CMOS | Cadence Virtuoso Tutorial | MK Jha"
"2-Input NAND Gate using CMOS | Transient Analysis |Cadence Virtuoso Tutorial | MK JHA | IIT Patna"
CMOS Inverter Transient and DC analysis | Very Basic | Opening Cadence Using xming and PuTTY | MKJHA
CMOS Inverter Transient and DC analysis | Very Basic | Opening Cadence Using xming and PuTTY | MKJHA
"CMOS Inverter Design | DC & Transient Analysis in Cadence Virtuoso | IIT Patna | MK JHA"
"NAND, NOR, XOR & XNOR using NMOS Pass Transistor Logic | Cadence Tutorial | IIT Patna | MK JHA"
"OR Gate using NMOS Pass Transistor Logic | Cadence Virtuoso Tutorial | IIT Patna | MK JHA"
"PMOS Id–Vgs Characteristics | Parametric Analysis for VDS in Cadence Virtuoso | IIT Patna | MK JHA"
"Multiplexer 2:1 Using NMOS Pass Transistor Logic | Cadence Virtuoso Tutorial | IIT Patna | MK JHA"
"AND Gate using NMOS Pass Transistor Logic | Cadence Virtuoso Tutorial | IIT Patna | MK JHA"
"PMOS Pass Transistor Logic in Cadence Virtuoso | Complete Simulation I IIT Patna | MK JHA"
"NMOS Pass Transistor Logic in Cadence Virtuoso | Complete Simulation | IIT Patna | MK JHA "
"Cadence Virtuoso Tutorial: PMOS ID vs VDS Plot & Parametric Analysis" | IIT Patna | MK JHA
"Cadence Virtuoso Tutorial: NMOS ID vs VGS Plot & Parametric Analysis" | IIT Patna | MK Jha
"Cadence Virtuoso Tutorial: NMOS ID vs VDS Plot & Parametric Analysis" | IIT Patna | MK JHA
"Cadence Virtuoso Setup: Open Using Xming & PuTTY | Step-by-Step Guide | IIT Patna |MK JHA
Poem | Madan Kumar Jha | alumnimeet'23 | B.C.E. Bhagalpur | Part 2 | Bhagalpur College of Engg.
Poem | Madan Kumar Jha | alumnimeet'23 | B.C.E. Bhagalpur | Part 2 | Bhagalpur College of Engg.
LOW PASS FILTER USING STM32F401RE NUCLEO BOARD || PART 1 || THEORY AND CODE EXPLANATION || IIT PATNA
LOW PASS FILTER USING STM32F401RE NUCLEO BOARD || PART 1 || THEORY AND CODE EXPLANATION || IIT PATNA
Poem | Madan kumar jha | alumnimeet'23 | B.C.E Bhagalpur | Part 1 | Bhagalpur College Of Engg.
Poem | Madan kumar jha | alumnimeet'23 | B.C.E Bhagalpur | Part 1 | Bhagalpur College Of Engg.