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Скачать или смотреть Inside the Box Episode 2: State Machines

  • Inside the Box
  • 2017-09-23
  • 76
Inside the Box Episode 2: State Machines
digital logicstate machinessequential logichardware designVHDLZybo
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Описание к видео Inside the Box Episode 2: State Machines

In this adventure we explore the workings of state machines since they occur within virtually all digital systems.

The example project is available on github and available via:
https://github.com/gau-veldt/InsideTh...

Yes I know the example source is called "AudioEcho" and this is because in the process of researching the Zybo's audio hardware it became evident that I2C (and I2S) communication is required. Communication protocols require state machines... (You get the idea :) thus the topic for today's adventure.

I've left mistakes in and agree with the camp that state mistakes are part of learning. This is only my second video so well, yeah, it is what it is.

The 1 state on the D flip flop state diagram should have the condition on the transition back to itself as D=1 (what was suddenly in the air I was breathing when I did that blunder???). My missteps on the ping pong example are also left in (also the ping pong main loop is over SIX states, NOT four).

Catch alls. I totally forgot to put that in. In the case statement for the state machine deciding on next state there needs to be a WHEN OTHERS clause (the "catch all"). If this is absent firstly the machine is less resilient to the machine starting from abnormal states (with a catch-all these will force the next state into one that is valid for the machine) and VHDL's clue for creating latches is process sections that don't cover all possible outcomes for the formally listed inputs so case statements missing the WHEN OTHERS clauses frequently create undesired latches (most VHDL compilers will also warn about these extra latches being created as well). The next state calculation should be combinational in nature (not sequential so defined on all input combinations) and to get a sequential component only the clock input should have no catch-all (for instance in my code there is handling of clock rising edges but nothing handling clock falling edges thus yielding a sequential element in the VHDL compiler). For a more concrete example on how the catch-all clauses are used please refer to this episode's source code (which has the necessary catch-all clauses).

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