Скачать или смотреть FPGA Polarfire Icicle Libero Part 4 - Add Custom Verilog

Getting started with the Libero FPGA synthesis tools. This is part 4 of
a series using the Libero tool set. After part 3 we should have downloaded
a bitstream to the Polarfire FPGA on the Icicle development board.

In this video we'll try to add our own custom Verilog logic into the refer
design. The custom design is the apb_blinky.v developed in example2 of our Verilog mini-series.

The Verlog code can be downloaded from GitHub at:
git clone https://github.com/bustedwing1/iveril...

The Verilog mini-series is at:
   • Verilog  


POLARFIRE SOC ICICLE LIBERO FPGA GATEWARE BRINGUP

Part 1
1. Download Icicle Kitg Reference Design from github using Git Bash
git clone https://github.com/polarfire-soc/icic...
2. Start Libero (assume Libero is already installed)
3. Setup IP repositories and Vault
4. Run TCL build script

Part 2
5. View the FPGA design with Libero
6. Run the Synthesis, Place&Route and Bit generation

Part 3
7. Download bitfile to the Icicle's Polarfire FPGA
8. Watch to see if LED blinks

Part 4 **** THIS VIDEO *****
9. Modify the design to blink an LED

Part 5
10. Modify C code to change the blink rate from default rate to a different rate

Part 6
11. Modify C code to control blink rate from PuTTY running on Laptop (via USB/UART)