Скачать или смотреть I Built a 32-bit RISC CPU, SoC, Toolchain, and Kernel From Scratch

I designed and implemented the entire stack from scratch: a 32-bit RISC architecture and CPU, SoC in Verilog, custom binutils and GCC ports, and a time-sharing kernel — and everything in this video is running on real FPGA hardware (PL-only).

In this demo, I show how it can actually be reproduced and what features it provides.

Architecture: https://github.com/Lamune-Amo/Architecture
Lamune kernel: https://github.com/Lamune-Amo/Lamune
Firmware: https://github.com/Lamune-Amo/Firmware
Binutils: https://github.com/Lamune-Amo/Binutils
GCC: https://github.com/Lamune-Amo/GCC
Documentation: https://github.com/Lamune-Amo/Document

Timeline
00:00 Building the toolchain
03:00 Building the kernel
04:13 AMO architecture
04:54 Live demo on FPGA