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This project report presents a complete hardware–software co-design workflow for developing a neural network accelerator capable of performing handwritten digit classification using the MNIST dataset. The work begins with the construction and training of a convolutional neural network (CNN) model in Python. This trained model serves as the algorithmic foundation for the accelerator design. The hardware portion of the project involves translating the core CNN operations - convolution, activation, pooling, fully connected layers, and classification - into synthesizable Verilog modules that can be deployed on FPGA hardware. The accelerator architecture is carefully organized to reflect the computational flow of the CNN while embracing hardware design principles such as pipelining, parallelism, and fixed-point arithmetic. Each component is developed as an independent hardware module and later integrated into a complete inference engine capable of processing MNIST images. A verification environment is constructed to simulate and validate the hardware implementation. Finally, the design is synthesized in the Xilinx Vivado design suite to assess resource utilization, performance characteristics, and timing behavior. The results demonstrate that a CNN-based accelerator can be successfully implemented in hardware to achieve efficient and accurate inference suitable for embedded and real-time systems. This report delivers a detailed account of the model development, design methodology, architectural decisions, hardware implementation, simulation-based verification, and performance evaluation, forming a cohesive and comprehensive study of neural network acceleration at the hardware level.