[Photolithography Part3] Alignment & Overlay

Welcome to the third installment of our detailed exploration into the world of optical photolithography for silicon wafer manufacturing. This episode zeroes in on the critical aspects of alignment and overlay in optical lithography, essential for maintaining the precision required in today's semiconductor industry. As devices become increasingly miniaturized, achieving and maintaining nanometer-scale accuracy in pattern placement is paramount. We will explore the sophisticated alignment and overlay control technologies utilized in ASML Twinscan systems, designed to meet these exacting standards. Below, you'll find the main chapters of this video. Click on any timestamp to jump directly to the desired section.

1. Introduction to Alignment & Overlay
[00:00] Introduction: Introduction to the series and what to expect in this episode.
[01:25] Alignment & Overlay Control: Exploring the fundamentals of alignment and overlay marks.
[04:40] Overlay Challenges: Discussing the limits of On-Product Overlay (OPO), Single Machine Overlay (SMO), and Total Measurement Uncertainty (TMU).
[08:25] Holistic Approach to Overlay Control
[12:05] Overlay Classification & Hierarchy: Understanding the origins of overlay errors.

2. Alignment & Leveling
[14:35] ASML TwinScan: Introducing innovative alignment control using two stages.
[17:35] Dual Stage Scanner Configuration: Highlighting the high system stability and precision of the TwinScan.
[21:55] Measurement Side for Alignment & Leveling in ASML TwinScan
[26:00] Life of a Wafer: Journey on the dual wafer stage in ASML TwinScan.
[28:50] Zeroing Process: Initializing overlay using interferometer or encoder methods.
[32:55] Alignment Equation: Explaining the alignment from reticle to stage and wafer in ASML TwinScan.
[35:40] Leveling Process: Discussing the Global Leveling Circle (GLC) for accurate scan points and Z-map for leveling control.
[38:20] Alignment Process: Exploring the Noinius principle for alignment control, Coarse Wafer Alignment (COWA), Fine Wafer Alignment (FIWA), and the global alignment approach.
[41:40] Advanced Alignment Techniques: Understanding ASML’s phase grating alignment mark, SMASH sensor, ATHENA/SMASH alignment marks.
[48:05] Alignment Mark Performance: Key performance indicators like WQ, MCC, ROPI, RPN.

3. Overlay Control
[52:30] Overlay Measurement and Modeling: Explaining overlay vectors, quantifying overlay errors, and modeling techniques.
[58:05] Overlay Linear Model: How overlay errors are linearly modeled with offset, interfield, and intrafield errors.
[1:01:40] Non-Linear High-Order Overlay Model: Exploring nonlinear modeling with Correction Per Exposure (CPE) and High-Order Process Correction (HOPC).
[1:05:10] Overlay Measurement Reliability: Discussing the reliability of overlay measurement tools through TMU, MAM time, and Q-merit.
[1:08:30] Overlay Marks (IBO vs DBO): Comparing image-based overlay (IBO) and diffraction-based overlay (DBO) marks.
[1:12:25] Process-Dependent Overlay Effects: How PVD and CMP processes affect overlay errors, and managing these with Misreading Correction (MRC).
[1:16:20] In-Device Metrology (IDM): The necessity for in-cell overlay to compensate for ADI-AEI and Metrology to Device Offset (MTD).
[1:19:45] Advanced Process Control (APC) for R2R: Utilizing feedback and feedforward schemes to minimize Run-to-Run overlay errors.
[1:23:30] EUV-DUV XMMO Issues: Addressing the challenges of crossed machine matched overlay (XMMO) between EUV and DUV ArF lithography with solutions like RegC and Litho Booster.

4. Wrap Up
[1:26:30] Review of Content: Including a mind map with keywords.