How to write Synthesizeable RTL

This video is intended to help novice digital logic designers get the hang of register-transfer level (RTL) coding. The video was created as supplementary material for my "Digital VLSI Design" course (Bar-Ilan University, course 83612), based on common mistakes made by students and my attempts to understand why they repeatedly do everything I tell them not to do in Lecture 2 of the DVD course. I realized that some of the concepts are not that clear and may need some extra emphasis and examples.

Note that you should not watch this video as a "beginners tutorial on Verilog". You will only know what I'm talking about if you've already learned Verilog syntax and then attempted to write some sequential code.

Good luck and looking forward to hearing your feedback.

Lecture slides can be found on the EnICS Labs web site at:
https://enicslabs.com/academic-course...

All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University