Скачать или смотреть USB 3.0 PHY IP Cores in 16FFC Process Technology

USB 3.0 PHY IP Cores in 16FFC is a transceiver which is provided for peripheral devices. The PHY is compliant with the USB 3.0 (USB SuperSpeed), USB 2.0 PIPE and UTMI specifications. The USB 3.0 PHY IP Cores transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high data throughput. The USB 3.0 PHY IP Cores comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, built-in self-test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.

Compliant with Universal Serial Bus 3.0 Specification the USB 3.0 PHY IP Cores in 16FFC, supports 5.0GT/s and 2.5GT/s serial data transmission rates and is also compliant with PIPE 3.1. The 16FFC process technology is also backward compatible with support for High-speed data transfer rate of 480 Mbps and Full-speed data transfer rate of 12 Mbps. With the support for 16-bit/ 32-bit parallel interface when encode/decode enabled and 20-bit when encode/decode bypassed the IP Cores has low jitter automatically calibrated oscillator for crystal-less mode.

Additional support of the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing and flexible reference clock frequency makes the IP Cores highly reliable and is able to achieve a Spread-Spectrum clock (SSC) generation and receiving of 5000ppm to 0ppm. The IP Cores also boasts a low IP area and low power consumption due to programmable transmit amplitude and De-emphasis, Low Frequency Periodic Signalling (LFPS) generation and detection, and a highly efficient L1 sub-state power management system.

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