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In this video, we explain the concept of Interrupts in 8085 Microprocessor in simple Bangla. Interrupts are crucial for handling urgent tasks by temporarily pausing the current program and executing a new one — a key feature in modern computing and embedded systems.

📌 What You’ll Learn:

0:00 – Introduction
0:08 – What is an Interrupt?
1:05 – Concept of Interrupt with Diagram


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CSE, ICT, and Diploma students
Beginners in microprocessors and digital electronics
Academic exams, viva & interview preparation

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Interrupts in 8085 Microprocessor

An interrupt is a signal that temporarily halts the normal execution of a program and diverts the microprocessor to perform a specific task. After completing the task, control returns to the main program. In the 8085 microprocessor, interrupts are categorized in several ways:

1. Hardware and Software Interrupts

Hardware Interrupts are received through physical pins of the microprocessor.
There are 5 hardware interrupts in 8085:

TRAP

RST 7.5

RST 6.5

RST 5.5

INTR

Software Interrupts are generated by specific instructions or mnemonics inserted in the program.
There are 8 software interrupts in 8085:

RST 0

RST 1

RST 2

RST 3

RST 4

RST 5

RST 6

RST 7

2. Vectored and Non-Vectored Interrupts

Vectored Interrupts have fixed memory addresses where the processor jumps to execute the corresponding subroutine.
The vector address is calculated using the formula: 8 × Interrupt Number.
Examples: TRAP, RST 7.5, RST 6.5, RST 5.5, etc.

Non-Vectored Interrupts do not have predefined addresses. The device must provide the address of the subroutine.
INTR is the only non-vectored interrupt in 8085.

3. Maskable and Non-Maskable Interrupts

Maskable Interrupts are those that can be disabled or ignored by the microprocessor using software instructions.
Examples: INTR, RST 7.5, RST 6.5, RST 5.5

Non-Maskable Interrupts cannot be disabled. These are used for critical tasks.
Example: TRAP, which is used in serious conditions like power failure. It has both level and edge triggering.

4. Interrupt Priority

When multiple interrupts occur simultaneously, the processor handles them according to a fixed priority order:

TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

5. Interrupt Service Routine (ISR)

An Interrupt Service Routine is a special block of code executed when a specific interrupt is triggered. After the ISR completes, control returns to the main program.

6. Triggering Mechanism (Level and Edge Triggering)

Triggering means activating a circuit to respond to signals. There are two main types of triggering:

Level Triggering:
The circuit becomes active when the clock or control signal stays at a certain level (HIGH or LOW).
Example: INTR, RST 6.5, RST 5.5

Edge Triggering:
The circuit activates at the moment the signal changes from LOW to HIGH (positive edge) or from HIGH to LOW (negative edge).
Example: RST 7.5

TRAP uses both edge and level triggering to make it highly reliable.

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