Скачать или смотреть UPC - EETAC - CSD – P7: Designing a 4-bit binary counter. Part 1: specifications.

Digital Circuits and Systems (CSD) (http://digsys.upc.edu) recording on how to proceed following the VHDL design flow from the specifications to the final prototype, conceiving a standard 4-bit presettable synchronous up/down binary counter planned as a synchronous sequential systems or finite state machine (FSM). This tutorial is available through the learning materials in P7 at the page: http://digsys.upc.edu/csd/P07/P7_T/Co...


The recording is composed of 4 videos. This is video part 1 on circuit specifications: symbol, function table, timing diagram, commercial circuit example 74LS169. Video part 2 on planning, part 3 on development and part 4 on testing will follow.



How does the CLK signal command state transitions and when?
How does a clear direct (CD) special signal work?
What is a parallel load operation?
What is count enabled or disabled?
What is counting up or down?
Which are the binary codes available at the outputs for n = 4?
What is the output signal TC16 used for?
How can this circuit work as a synchronous data register?

How counters can be expanded? For instance, how to use several standard counter_mod16 to construct a counter_mod448?


And many more questions from the general mind map at: http://digsys.upc.edu/csd/P07/P7_Desi...