#39 Finite state machine(FSM) | Mealy state machine |sequential logic design |writing FSM in verilog

Finite state machine ( FSM ) || Mealy state machine || important concept in logic design || sequential logic design

in this verilog tutorial Mealy based state machine has been covered in details. FSM are used to design controller in digital system. FSM are one of the most important concept in digital logic design. In this video only mealy State machine has been explained. writing verilog code for FSM has been explained in details with simple explanation

Lesson-1 Why verilog is a popular HDL    • #1 Why verilog is a popular HDL | pro...  
Lesson-2 Operators in verilog(part-1)    • #2  Operators in Verilog ( part -1 ) ...  
Lesson-2 Operators in verilog(part-2)    • Operators in Verilog ( part -2 ) | Ho...  
Lesson-2 Operators in verilog(part-3)    • Operators in Verilog( Part-3)  | How ...  
Lesson-3 Syntax in verilog    • #3  Syntax in Verilog  | Identifier, ...  
Lesson-4 Data types in verilog    • #4 Data types in verilog | wire, reg,...  
Lesson-5 Vector and Array in verilog    • #5 {Error:check description} Vector a...  
Lesson-6 Modules and port in verilog    • #6  Module and port declaration in ve...  
Lesson-7 Gate level modelling in verilog    • #7  Gate level modeling and structura...  
Lesson-8 Dataflow Modeling in verilog    • #8  Data flow modeling in verilog | e...  
Lesson-9 Behavioral Modeling in verilog    • #9  Behavioral modelling in verilog |...  
Lesson-10 Structural Modeling in verilog    • #10  How to write verilog code using ...  
Lesson-11 always block in verilog    • #11  always block in Verilog || proce...  
Lesson-12 always block for combinational logic    • #12 always block for combinational lo...  
Lesson-13 sequential logic in design    • #13{Mistake:check description}sequent...  
Lesson-14 always block for sequential logic    • #14 always block for sequential logic...  
Lesson-15 Difference between latch and flip flop    • #15  Difference between Latch and Fli...  
Lesson-16 Synchronous and Asynchronous RESET    • #16(MISTAKE-Read Description) Synchro...  
Lesson-17 Delays in verilog    • #17 Delays in verilog | Rise time, fa...  
Lesson-18 Timing control in verilog    • #18 Timing control in verilog | Delay...  
Lesson-19 Blocking and Nonblocking assignment    • #19 Blocking vs Non Blocking assignme...  
Lesson-20 inter and intra assignment delay in verilog    • #20 Inter and intra assignment delay ...  
Lesson-21 Why delays are not synthesizable    • #21 Why delays are not synthesizsble ...  
Lesson-22 TESTBENCH writing in verilog    • #22 How to write TESTBENCH  in verilo...  
Lesson-23 Multiple always block in verilog    • #23 Multiple ALWAYS block in verilog ...  
Lesson-24 INITIAL block in verilog    • #24 INITIAL block in verilog | use of...  
Lesson-25 Difference between INITIAL and ALWAYS block in verilog    • #25 Difference between ALWAYS and INI...  
Lesson-26 if else in verilog    • #26 if-else in verilog |conditional s...  
Lesson-27 CASE statement in verilog    • #27 "case" statement in verilog | if-...  
Lesson-28 CASEX and CASEZ in verilog    • #28 casex vs casez in verilog | Expla...  
Lesson-29 FOR loop in verilog    • #29 "for" loop in verilog || Hardware...  
Lesson-30 WHILE loop in verilog    • #30 "while" loop in verilog || Hardwa...  
Lesson-31 FOREVER in verilog    • #31 " forever " in verilog || How to ...  
Lesson-32 REPEAT in verilog    • #32 " repeat " in verilog || realtime...  
Lesson-33 GENERATE in verilog    • #33 "generate" in verilog | generate ...  
Lesson-34 FORK-JOIN in verilog    • #34 " fork and join " in verilog || p...  
Lesson-35 named block in verilog    • #35 Named block in verilog || verilog...  
Lesson-36 TASK in verilog    • #36 (MISTAKE-Read Description) TASK i...  
Lesson-37 FUNCTION in verilog    • #37 (MISTAKE-Read Description) FUNCTI...  
Lesson-38 WIRE vs REG in verilog    • #38 Wire vs Reg | when to use wire an...  
Lesson-39 FSM-MEALY state machine in verilog    • #39 Finite state machine(FSM) | Mealy...  
Lesson-40 FSM- MOORE state machine in verilog    • #40 Finite state machine(FSM) | Moore...  


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