How to create a Finite-State Machine in VHDL

Learn how to implement an algorithm in VHDL using a finite-state machine (FSM).

The blog post for this video:
https://vhdlwhiz.com/finite-state-mac...

A finite-state machines or FSM for short, is a construct whose next behavior is determined not only by the inputs, but also by its previous state.

State machines are typically used in FPGAs and ASICs to implement algorithms or protocols. As a VHDL designer it is important to understand this very important concept of digital design.

State machines can be implemented in different ways. Most common is the one-process state machine. The state of the FSM is represented by a signal with an enumerated type. The State signal is then used as selector to a Case-When statement in a clocked process.

When a predefined condition is met, the state will be changed. Thus, the FSM will enter a different branch of the Case-When statement at the next iteration of the process.