Скачать или смотреть 🔥🔥WEEK 4“Programming" ANSWERS🔥🔥 HARDWARE MIDELING USING VERILOG (NPTEL) programming in description

In the programming questions all the test cases are passed but the approach is not according to the question if anyone finds the correct solution plz upload in the comments.


please try to solve it by your own instead of direct copying and pasting it will create a better understanding it is for the students who have tried it once and have little amount of doubts .
1)module mux4x1 (in, sel, out);
input [3:0] in;
input [1:0] sel;
output reg out;
always@(*) begin
case(sel)
2'b00:out=in[0];
2'b01:out=in[1];
2'b10:out=in[2];
2'b11:out=in[3];
default:out=1'bx;
endcase
end
endmodule

2)module bus_multiplexer (D3,D2,D1,D0,SEL,DBUS);
input [15:0]D3,D2,D1,D0;
input [1:0] SEL;
output reg [15:0]DBUS;
always@(*)
begin
case(SEL)
2'b00:DBUS=D0;
2'b01:DBUS=D1;
2'b10:DBUS=D2;
2'b11:DBUS=D3;
endcase
end
endmodule