CompArch - Chapter 8 - Memory Systems - Prob.2

Описание к видео CompArch - Chapter 8 - Memory Systems - Prob.2

#cache #Totalcachesize #ARM #wordaddressing #patterson #computerorganization
This exercise examines the effect of different cache designs, specifically comparing fully associative cache to the direct-mapped cache.
A processor (using a big-endian notation) has the following sequence of word address. (a) Assuming direct-mapped cache, containing 1-word blocks and a total size of 16 words. Show the final state of the cache in the given table. (b) Repeat part (a) with assuming fully associative cache, containing 1-word blocks and a total size of 16 words. Show the final state of the cache in the given table.

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