SDC 2023 - PCIe® 7.0 Specification: 128 GT/s Bandwidth for Future Data-Intensive Markets

Описание к видео SDC 2023 - PCIe® 7.0 Specification: 128 GT/s Bandwidth for Future Data-Intensive Markets

For the past three decades, PCI-SIG® has delivered a succession of industry-leading PCI Express® (PCIe®) specifications that remain ahead of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in storage applications and diverse market segments. In 2022, PCI-SIG announced the PCIe 7.0 specification is targeted for release to members in 2025. The feature goals of the forthcoming specification include doubling the raw data rate of the PCIe 6.0 specification to 128 GT/s raw data rate and up to 512 GB/s bi-directionally via x16 configuration, PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding, improved power efficiency, and maintaining backwards compatibility with all previous generations of PCIe technology. This session will update attendees on the feature goals of the PCIe 7.0 specification and the benefits for diverse applications, including 800 G Ethernet, AI/ML, Cloud and Quantum Computing; and data-intensive markets like Hyperscale Data Centers, High-Performance Computing (HPC) and Military/Aerospace. Attendees will also receive updates on the PCIe 6.0 specification market adoption and use cases, in addition to an overview of the current status of the PCIe 5.0 Compliance Program.

Learning Objectives
How PCIe 7.0 will deliver 128 GT/s transfer rates, while continuing to innovate with new features like improved power efficiency, Pulse Amplitude Modulation with 4 levels (PAM4) signaling, low-latency Forward Error Correction (FEC) and Flit-based encoding
The benefits of the PCIe 7.0 specification in diverse applications, including 800 G Ethernet, AI/ML, Cloud and Quantum Computing; and data-intensive markets like Hyperscale Data Centers, High-Performance Computing (HPC) and Military/Aerospace
Updates on the PCIe 6.0 specification market adoption and the PCIe 5.0 Compliance Program

Presented by Debendra Das Sharma, Intel

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