Digital-on-top Physical Verification (Fullchip LVS/DRC) - Part 1

This is a 6-part lecture series on how to run physical verification, i.e., LVS and DRC, on a block created with a digital implementation flow (place and route). The first five parts of the lecture series is dedicated to the "digital-on-top" (a.k.a. "Fullchip") layout-vs.-schematics (LVS) flow and the final part overviews DRC and chip finishing.

The content of the lecture series is as follows:
Part 1: Introduction to Digital-on-Top LVS
Part 2: Creating the LVS-ready Verilog Netlist
Part 3: Translating the Verilog netlist into SPICE
Part 4: Extracting the LVS-ready Layout netlist
Part 5: Running LVS comparison
Part 6: Fullchip DRC and Chip Finishing

The lecture series is given by Dr. Adam Teman of the EnICS Labs Impact Center at Bar-Ilan University, based entirely on personal experience. The overview is demonstrated on a Cadence-based implementation flow (Genus+Innovus) with DRC/LVS running on Calibre tools. The designs shown in the demonstration are proprietary of BIU and no vendor or technology specific details are revealed.

The lecture slides can be found on my website https://www.eng.biu.ac.il/temanad/oth...

Additional lectures by Dr. Adam Teman can be found at https://www.eng.biu.ac.il/temanad/tea... or on my YouTube channel ‪@AdiTeman‬ .