FreeBSD: FPGA development of RISC-V 32bit CPU, and buffer overflow demo

I have been working on a FPGA (Field Programmable Gate Array) project over the last days. My own personal goal is to better understand the RISC-V instruction set, and to explore FPGA development under FreeBSD. In this video, I give details about my RISC-V project, go briefly over the architecture, the Verilog and the C files. I show how to use Icarus Verilog and GTKWave to simulate the design. Of course, I like to do things "my way".

In this video, I also spend some time showing how to do a buffer overflow on a 32bit RISC-V CPU. Yes... I really like to explore those "dark corners" :-)
The nice thing is that, since I am doing a full bit-level simulation of the CPU, although I am not showing these details in the video, I can "see" exactly what happens at all details and very deep in the CPU...

In a further video, I will explore the programming of a physical FPGA device, writing my own program, and loading it up into the hardware. Stay tuned for more... (maybe also do the buffer overflow demo, but on real hardware? :-)

As always, if you like the video, please give it a thumbs up!
Constructive comments are more then welcome.

Please notice - I make these videos on my free time and the target audience is myself. If you like the video - awesome, I am glad you did; if you do not like the video, there are plenty of others on youtube that you can watch... :-)

#FreeBSD #FPGA #iverilog #gtkwave