Скачать или смотреть Write RTL Testbench to Display Output on Console Window in Verilog and VHDL. Break/Exit Simulation

#Write #RTL #Testbench to #Display #Output on #Console/#Transcript #Window in #Verilog and #VHDL. #Break/#Exit #simulation

SV RTL testbench:

module testbench;

reg stop;
reg [15:0] cycles;

initial begin
stop = 1'b0;
cycles = 16'b0;
$timeformat(-9, 2, " ns", 15); // to display ns with time
end

always @(negedge clk)
begin
cycles ＜= cycles + 1;
if (stop)
begin
//$display("Time:%t Instance: /%m ",$time);// %m to see module name
//$display("** Note:%d: pc=%d, stop program",
//cycles, pc);
$strobe("Time:%t Instance: /%m ",$time);
$strobe("** Note:%d: pc=%d, stop program",
cycles, pc);
//$write("Time:%t Instance: /%m \n",$realtime);
//$write("** Note:%d: pc=%d, stop program\n",
//cycles, pc);
$finish;//to end simulation
//$stop;
end
else
begin
if (~power)
begin
//$display("Time:%t Instance: /%m ",$time);
//$display("** Note:%d: pwr=%b, pc=%d, npc=%d",
//cycles, power, pc, next_pc);
$strobe("Time:%t Instance: /%m ",$time);
$strobe("** Note:%d: pwr=%b, pc=%d, npc=%d",
cycles, power, pc, next_pc);
//$write("Time:%t Instance: /%m \n",$realtime);
//$write("** Note:%d: pwr=%b, pc=%d, npc=%d\n",
//cycles, power, pc, next_pc);
end
else
begin
if (stop_en)
begin
//$display("Time:%t Instance: /%m ",$time);
//$display("** Note:%d: pwr=%b, pc=%d, npc=%d, stop",
//cycles, power, pc, next_pc);
$strobe("Time:%t Instance: /%m ",$time);
$strobe("** Note:%d: pwr=%b, pc=%d, npc=%d, stop",
cycles, power, pc, next_pc);
//$write("Time:%t Instance: /%m \n",$realtime);
//$write("** Note:%d: pwr=%b, pc=%d, npc=%d, stop\n",
//cycles, power, pc, next_pc);
stop = 1;
end
else
begin
if (branch_en)
begin
//$display("Time:%t Instance: /%m",$time);
//$display("** Note:%d: pwr=%b, pc=%d, npc=%d, branch to %d",
//cycles, power, pc, next_pc, branch_pc);
$strobe("Time:%t Instance: /%m ",$time);
$strobe("** Note:%d: pwr=%b, pc=%d, npc=%d branch to %d",
cycles, power, pc, next_pc, branch_pc);
//$write("Time:%t Instance: /%m \n",$realtime);
//$write("** Note:%d: pwr=%b, pc=%d, npc=%d, branch to %d\n",
//cycles, power, pc, next_pc, branch_pc);
end
else
begin
//$display("Time:%t Instance: /%m ",$time);
//$display("** Note:%d: pwr=%b, pc=%d, npc=%d, inc_pc %d",
//cycles, power, pc, next_pc, pc + 1);
$strobe("Time:%t Instance: /%m ",$time);
$strobe("** Note:%d: pwr=%b, pc=%d, npc=%d, inc_pc %d",
cycles, power, pc, next_pc, pc + 1);
//$write("Time:%t Instance: /%m \n",$realtime);
//$write("** Note:%d: pwr=%b, pc=%d, npc=%d, inc_pc %d\n",
//cycles, power, pc, next_pc, pc + 1);
end
end // else: !if(branch_en)
end // else: !if(power)
end // else: !if(stop)
end // always @ (negedge clk)

endmodule


VHDL RTL testbench:

entity testbench is
end testbench;

architecture behav of testbench is

signal cycles:std_logic_vector (15 downto 0):=x"0000";
signal stop:std_logic;

begin

Process(clk)
begin
if FallING_EDGE (clk) then
cycles ＜= cycles + 1;
if stop = '1' then
report INTEGER'IMAGE(to_integer(unsigned(cycles))) & " :" &
" pc=" & INTEGER'IMAGE(to_integer(unsigned(pc))) &
" stop program";
assert false report "Test: OK" severity failure;
else
if power = '0' then
report INTEGER'IMAGE(to_integer(unsigned(cycles))) & " :" &
" pwr=" & INTEGER'IMAGE(to_integer(unsigned'("" & power))) &
" pc=" & INTEGER'IMAGE(to_integer(unsigned(pc))) &
" npc=" & INTEGER'IMAGE(to_integer(unsigned(next_pc)));
else
if (stop_en = '1') then
report INTEGER'IMAGE(to_integer(unsigned(cycles))) & " :" &
" pwr=" & INTEGER'IMAGE(to_integer(unsigned'("" & power))) &
" pc=" & INTEGER'IMAGE(to_integer(unsigned(pc))) &
" npc=" & INTEGER'IMAGE(to_integer(unsigned(next_pc))) &
" stop";
stop ＜= '1';
else
if (branch_en = '1') then
report INTEGER'IMAGE(to_integer(unsigned(cycles))) & " :" &
" pwr=" & INTEGER'IMAGE(to_integer(unsigned'("" & power))) &
" pc=" & INTEGER'IMAGE(to_integer(unsigned(pc))) &
" npc=" & INTEGER'IMAGE(to_integer(unsigned(next_pc))) &
" branch to " & INTEGER'IMAGE(to_integer(unsigned(branch_pc)));
else
report INTEGER'IMAGE(to_integer(unsigned(cycles))) & " :" &
" pwr=" & INTEGER'IMAGE(to_integer(unsigned'("" & power))) &
" pc=" & INTEGER'IMAGE(to_integer(unsigned(pc))) &
" npc=" & INTEGER'IMAGE(to_integer(unsigned(next_pc))) &
" inc_pc " & INTEGER'IMAGE(to_integer(unsigned(pc + 1)));
end if;--if branch_en
end if; -- else: !if(stop_en)
end if;-- !if(power)
end if;-- if(stop ='1')
end if;-- if falling edge (clk)
end process;-- process begin

end behav;