LMK04800 Clock Jitter Cleaner/Distribution Demo

Alan demonstrates the LMK04800 clock jitter cleaner and distribution family including: * Ultra-Low RMS Jitter Performance using low-cost external crystal * 111 fs RMS jitter (12 kHz to 20 MHz) * 123 fs RMS jitter (100 Hz to 20 MHz) * Dual Loop PLLatinum PLL Architecture * PLL1 * Integrated Low-Noise Crystal Oscillator Circuit * Holdover mode when input clocks are lost * Automatic or manual triggering/recovery * PLL2 * Normalized [1 Hz] PLL noise floor of -227 dBc/Hz * Phase detector rate up to 155 MHz * OSCin frequency-doubler * Integrated Low-Noise VCO * 2 redundant input clocks with LOS * Automatic and manual switch-over modes * 50% duty cycle output divides, 1 to 1045 (even and odd) * LVPECL, LVDS, or LVCMOS programmable outputs * Precision digital delay, fixed or dynamically adjustable * 25 ps step analog delay control * 14 differential outputs, Up to 26 single ended * Up to 6 VCXO/Crystal buffered outputs * Clock rates of up to 1536 MHz * 0-delay mode * Three default clock outputs at power up * Multi-mode: Dual PLL, single PLL, and clock distribution * Industrial Temperature Range: -40 to 85 ?C * 3.15 V to 3.45 V operation * Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)