Building 65c02 from scratch in Verilog: Why on earth???

The 6502 was the king of early days of personal computers. No project building those computers can go forward without it. Which made the fact that I didn't find a Verilog implementation I could use a problem.

So I'm building one myself.

In this video I'm going over the design of the heart of any CISC CPU: the instruction decoder (the microcode).


Project CompuSAR aims at building 70's and 80's computers on a low-end FPGA. Most of the project works from scratch, and this channel half documents the progress, half teaches about the concepts that come into play when designing such a system.

You can view the whole project, in sequence, in the play list here:    • Building 65c02 from scratch in Verilo...  

This stage of the project is about designing the 6502 CPU on FPGA. You can watch only the 6502 videos, in sequence, at the play list here:    • Building 65c02 from scratch in Verilo...  

Follow me on twitter:   / shacharshemesh  


Table of contents:
00:00 Why 6502 and why write our own
01:34 Scope of work
02:16 Different opcodes are not that different
03:49 Table the opcode discussion
05:50 The instruction register
08:44 The instruction decoder in Verilog
11:18 Splitting the instruction register
12:25 Adding a new opcode
13:10 Manually verifying the result
21:21 Automatic verification of the result
27:15 Future plans

Useful links:
Source code for project: https://github.com/CompuSAR/wd65c02

My Twitter account:   / shacharshemesh  

WD65C02S data sheet: http://westerndesigncenter.com/wdc/do...

Xilinx Vivado: https://www.xilinx.com/products/desig...

The Spartan-7 board I'm using: https://www.aliexpress.com/item/40011...