Live: 6502 Flags and Addressing Modes: Writing microcode for an FPGA 6502

Stream starts at 23-June-2024 at 5pm GMT.

The 6502 is a CISC 8 bit CPU. We'll be implementing it as a synchronous bus FPGA module. In this session the internal architecture is (hopefully) finished or almost finished, and all that's left is to write the microcode that implements the actual opcodes.

We'll continue implementing opcodes in the order in which the test program uses them. Next up are some direct processor flags manipulations and also begin to implement the different CPU addressing mode.

I'd like to thank my Patreon BBC Micro level supporter, Yehuda T. Deutsch.
You, too, can support my work on Patreon:   / compusar  

Discord server invite:   / discord  

Code written during the stream is available at https://github.com/CompuSAR/sar6502-sync
6502 block diagram is at https://www.witwright.com/DonPub/6502...
visual6502 site: https://visual6502.org
WDC datasheet: https://www.westerndesigncenter.com/w...