18nm finFET nfin = 1, A = y = 0 Vro V = 0 25 0 19 VosAT V = 0 2 0 22 Kerr AV = 230 130 nMOS pMOS

18nm finFET (nfin = 1), A = y = 0 Vro (V) = 0.25 - 0.19 VosAT (V) = 0.2 - 0.22 Kerr (A/V) = 230 130 nMOS pMOS Problem 1. You are asked to design a non-inverting buffer in 18-nm finFET CMOS technology to drive a large capacitive load (i.e. CL = 20 pF). Assume that the first inverter is an inverter with nfin = 2 and nfinp = 3. The intrinsic propagation delay of the inverter is tpo = 8 ps. The optimum stage effort, hopt, for this technology is hopt = 3.6. a. Determine the optimum number of stages required for this buffer. b. Determine transistor sizes in each inverter. c. What is the delay of this buffer? Cin = 2 fF CL = 20 pF

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