Скачать или смотреть Constraints and Routing for a Successful DDR3/DDR4 Design

Setting up the proper design constraints and following these constraints when routing the board is critical for the high speeds involved in Double Data Rate (DDR) designs. In this webinar we will discuss the routing constraints required for a DDR3/DD4 design. We will demonstrate the organization of these constraints using Mentor’s Constraint Editing System (CES) in PADS Professional®, a fully integrated constraint-driven design methodology that reduces design costs and time-to-market by automating design rules communication.

We then go on to demonstrate routing the DDR design circuits and how PADS Professional helps you keep increasingly dense, complex PCB designs strictly constrained to design rules. We will highlight the routing techniques that enable you to have more control and significantly greater productivity with manual-route quality.