Скачать или смотреть Clock Controller Unit Design Metrics: Area, Power, SW Flexibility Congestion Impacts at System Level

Full title: Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level

Presented at DVCon Europe 2020

The aim of this paper is to highlight how same complex Multi-Clock Digital IP System is impacted by different RTL design strategies of its dedicated Clock Control Unit (CCU). Area, Power, Software Flexibility and Routing Congestion have been analyzed and compared. Digital Front-End stage has entirely covered from design to logic synthesis by using DC (Design Compiler), DV (Design Vision) tools and PC (Power Compiler). Outcome results of this paper provide metrics and guidelines to CCU digital designers. The quality of being novel is the fact that current literature shows how clocks impact the design, but all analysis has been made with assumptions and mathematical models have been used to shape design features. This work, instead, picks a real example of edge-cutting Digital Sub-System with +300k flops and all design features such as bus infrastructure linking complex internal cores. RTL also includes DFT logic used to test all the faults of the chip on silicon.

Michele Chilla, Leonardo
Gobbi – Qualcomm Ireland

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