How a CPU Instruction Decoder and Instruction Execution Works

In this video, we investigate how Instruction Decoding and Instruction Execution gets carried out inside a CPU or Microprocessor.

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00:00 Introduction
01:20 Fetch Instruction from Memory
01:50 Decode the Instruction
02:48 The Boolean Logic
04:55 The CPU Internal Data Bus
05:25 To the Control Unit...
06:36 Memory Types Used in Computers
08:46 Implementing the Control Unit via a ROM Array
12:22 CPU Microprogramming
12:45 The Microcode or Microinstructions for the Add Instruction
13:11 Summary & Outro


The Videos of this Series :

1: How a Computer Works: Introduction to Playlist -Understanding Core Fundamentals of Computer Hardware
   • How a Computer Works: Introduction to...  

2 : How a Computer CPU or microProcessor Works - I - ( Core Fundamentals of Electrical circuit of a CPU)
   • How a Computer CPU or microProcessor ...  

3: How a CPU Instruction Decoder and Instruction Execution Works
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4. How Memory Address Decoding Works
   • How Memory Address Decoding Works  

5. How Memory Address Decoding Works (Part 2)
   • How Memory Address Decoding Works (Pa...  

6: How Computer Memory Works (The Core Fundamentals of Electrical Circuit of DRAM)
   • How Computer Memory Works (The Core F...  

7: How Flat Panel Display Electrical Circuit Works. (Understanding the Core Fundamentals)
   • How Flat Panel Display Electrical Cir...  

8: Basic Fundamentals of Number Systems
   • Number Systems: The Basic Fundamentals  

NOTES 1:
Those whom are familiar with Assembly Language might have noticed that the Add instruction we have implemented in our CPU to be a bit different from say the standard Add instruction, which would usually Add either two values already present in Internal Registers or Add a Value stored at a Memory Location, to a Value stored in a Register etc.

The reasons for implementing a bit non-Standard Add construct were:
1.1. To highlight that, there are ample cases, where the Program Counter has to be incremented more than once, during the execution of a Single Instruction. Aka the Next Instruction to be Executed, does not necessarily has to be at the Next Memory Location.

1.2. To highlight that if/when one goes for a CPU design, there is no set and fast rules, that one is required to follow, UNLESS one is implementing an Industry Standard Instruction set.

The issues associated with Implementing a non Standard Instruction set, is a totally different topic altogether. For example, most all software may/might have to be re-implemented/re-written/... to run with this new Instruction Set Architecture (ISA) etc.

Thus in many cases, when a new ISA is implemented, one of the first softwares to be ported or implemented on that environment, would be a C/C++ compiler, such of gcc. And then using that C/C++ compiler, one can compile/port the other softwares, onto the new ISA.

NOTES 2:
Many Instruction Decoders, one finds in Production Level or Industrial Microprocessors, do have a few Optimization Techniques to Uniquely Identify as to whether the Instruction is an Arithmetic Operation or as to whether it's a Logic Operation or... etc.

These optimizations do play a role in speeding up the execution process, as well as optimizing the Logic Designs.

Our Bare Bone Basic CPU, will not go into these optimization techniques at this stage, until the Core Fundamentals are covered to sufficient details...