Compilation - Part Five: Object Code Generation

This is part five of a series of videos about compilation. Part five is about generating machine code from intermediate representations of a program, such as syntax trees or three address code (TAC). It covers instruction selection, register allocation and assignment and instruction ordering. Peephole optimisation of machine code is also mentioned, although techniques for removing duplicate sub-expressions and dead code, copy propagation, constant folding and flow control optimisation are covered in more detail in the preceding video. This video demonstrates the principles of object code generation using a simple model machine language whose commands are depicted in assembly code; a reasonable depiction because there is a one to one correspondence between assembly code and binary machine code. The generation of load, store, computation and branching instructions is shown. Register allocation and assignment using address descriptors and register descriptors is illustrated with an example. The influence of processor architectures such as RISC and CISC on instruction selection is also discussed, along with a technique for instruction selection known as tree tiling, using a tree translation scheme. As you will see as you watch this series, compilation involves a diverse range of themes in the field of computer science including high and low level programming paradigms, the definition of context free grammars, the application of dynamic data structures such as stacks, linked lists, hash tables, graphs and trees, memory management, processor architectures, and more. This series will give you an insight into some of the concepts and features that are typical of many compilers.