Скачать или смотреть 2022 LLVM Dev Mtg: RISC-V Sign Extension Optimizations

2022 LLVM Developers' Meeting
https://llvm.org/devmtg/2022-11/
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RISC-V Sign Extension Optimizations
Speaker: Craig Topper
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Slides: https://llvm.org/devmtg/2022-11/slide...
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The 64-bit RISC-V target is the only one in-tree that does not have 32-bit sub-registers or i32 as a legal type. Many instructions have forms that sign extend their result by copying bit 31 into bits 63:32. Only loads are able to implicitly zero bits 63:32. Some instructions such as comparisons only operate on all 64 bits and require smaller values to be extended. The ABI also requires 32-bit arguments and return values to be sign extended to 64 bits. Making good use of the implicit sign extending instructions is important to generate optimal assembly from C code where 32-bit integers are prevalent.

This talk will discuss how this differs from other 64-bit targets, how single basic block SelectionDAG makes this difficult, and how optimizations that are good for other 64-bit targets may be harmful for RISC-V. It will cover the optimizations and custom passes that have been added to improve the generated code and ideas for future enhancements.

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