oreboot on VisionFive 2 006: DRAM init done

During this video series, we develop firmware in Rust, targeting application processors. Continuing from the season on the VisionFive 1 board, we now work with the VisionFive 2, featuring the StarFive JH7110 RISC-V SoC.

In this video, after a quick look at the RISC-V ecosystem landscape, we walk through the entire DRAM init code that is now finished and working fine. With the technical reference manual, we see how the clock setup makes sense, and eventually run our code in order to end up executing a payload and waking up the secondary harts.

Previous series on the VisionFive 1:
   • oreboot on VisionFive 1 001: Unboxing...  

References:
https://github.com/oreboot/oreboot/pu...
https://github.com/starfive-tech/u-bo...
https://doc-en.rvspace.org/JH7110/PDF...
https://landscape.riscv.org/
https://landscape.riscv.org/card-mode
https://iwp9.org/#prg
https://www.synopsys.com/designware-i...
https://people.inf.ethz.ch/omutlu/