Now it's 3: Huawei, SMIC shock the semiconductor industry again by introducing 3-nanometer chip

Huawei, SMIC and SiCarrier have patented a new process for developing chips with 3-nanometer class nodes. Industry experts were stunned when Huawei "brute-forced" the use of quadruple patterning to build 5-nanometer chips; now the company and its partners have further improved their applications by building chips at 3-nm.

Resources and links:

Tom's hardware, SMIC and Huawei could use quadruple patterning for China-made 5nm chips: Report
https://www.tomshardware.com/tech-ind...

Tom's Hardware, Huawei patent reveals 3nm-class process technology plans — China continues to move forward despite US sanctions
https://www.tomshardware.com/tech-ind...

Bloomberg, Huawei Tests Brute-Force Method for Making More Advanced Chips
https://www.bloomberg.com/news/articl...

SiCarrier's Patent Application: Method for manufacturing self-aligned quadruple patterned semiconductor apparatus, and semiconductor apparatus
https://patents.google.com/patent/WO2...

SHOCKING! SMIC to build 5nm chip for Huawei without EUV; foundry is third largest in the world
https://www.phonearena.com/news/smic-...

Center for Strategic and International Studies, In Chip Race, China Gives Huawei the Steering Wheel: Huawei’s New Smartphone and the Future of Semiconductor Export Controls
https://www.csis.org/analysis/chip-ra...

Closing scenes: Kunming Stone Forest Park, Yunnan