Скачать или смотреть A Simplified Synchronous Dynamic RAM Controller

Successfully implemented a simplified synchronous dynamic RAM controller circuit for a happy client. In this video you will learn about this controller circuit which has the following specifications:
The inputs to the circuit are a 22 bit address (ADDRIN), a read signal (RD), a write signal (WR), and an enable signal (CS). This circuit does not function until CS becomes 1, then the 22-bit ADDRIN is loaded in as a row address (bits 19 to 10) and a column address (bits 9 to 0) registers. A busy signal
“Ready” is sent back to the Host. The Read and Write, address lines 20 (B0) and 21 (B1) signals are “stored” in the Controller. Subsequently, the row address is outputted at (ADDROUT (10 bits wide)) along with the row address strobe (RAS) signal (active low) which is generated one clock cycle later. The RAS signal is outputted according to rules in table 1 to enable accessing different memory banks. Then, the column address is outputted along with the column address strobe signal (CAS), which is generated one clock cycle later. Finally, if the operation is a write operation (RD = 0, WR = 1), then the WE output is 1. Otherwise, for a read operation (RD = 1, WR = 0), the WE output remains 0. The controller returns to the initial state after generating all the required signals.

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