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VLSI Physical Verification
VLSI Layout Verification
Physical Verification is an important step in VLSI design cycle. It’s also called as Layout Verification.

VLSI Physical (Layout) Verification

 Physical (Layout) Verification is the process of verifying the layout designed, honoring the foundry design rules for proper fabrication & yield in the particular technology.

 Physical Verification includes DRC, LVS, PERC, ESD, MPT, DFM checks like fill generation, Litho Checks, Pattern Matching checks, LVL, VRC etc.,.

 Tools mainly used in the PV domain are Calibre(Siemens), ICV(Synopsys).



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