Webinar - Infineon TriCore™ AURIX™ TC3xx HSM - Debug & Timing Analysis

This webinar is focusing on debugging and timing analysis of the HSM (Hardware Security Module) core of the Infineon TriCore™ AURIX™ TC3xx family.

00:00 Introduction
01:30 Agenda
02:27 Introduction to HSM
03:38 HSM Debug System
05:11 winIDEA HSM Operation
08:03 winIDEA Demo Mode
09:13 Live Demo – Tool Set Up
10:37 Use Case 1: Debugging HSM Core - Theory
11:45 Use Case 2: Timing Analysis – Instrumenting HSM code and trace using MCDS data trace - Theory
15:50 Use Case 3: Timing Analysis – Sampling-based Profiling – Theory
18:40 Enabling winIDEA Demo Mode
21:29 Use Case 1: Debugging HSM Core – winIDEA Demo
23:17 Use Case 2: Timing Analysis – Instrumenting HSM code and trace using MCDS data trace – Theory
27:44 Use Case 3: Timing Analysis – Sampling-based Profiling – winIDEA
31:24 Conclusion
32:05 Q&A
32:35 Q1: What if I locked the chip?
33:19 Q2: USB programming in winIDEA – manually and automated via the API
33:59 Q3: Enabling secure boot features
36:12 Q4: Program cycles, UCB (User Configuration Blocks), and bricking the device
37:07 Q5: Accuracy of the results of sampling-based profiling
38:44 Q6: Synchronization of Aurix and HSM core, and stopping the HSM after a host reset
40:15 Q7: UCB configuration, boot mode – first HSM?
42:06 Q8: Configuration of sampling-based profiling
42:48 Q9: Can a beginner rely on winIDEA to avoid locking a device?
45:08 Outro