Скачать или смотреть How a Signal is different from a Variable in VHDL

Learn how to declare a signal in VHDL, and see what makes it different from a variable. Although very much alike, signals and variable behave completely different for some use cases.

Blog post for this video:
https://vhdlwhiz.com/signals-vs-varia...

Signals are declared in the declarative region of the architecture. That is directly before the first "begin" keyword in .vhd file containing the architecture. The scope of a signal is within the architecture, meaning that it can be accessed by any of the processes in that architecture.

Variables, on the other hand, are declared in the declarative region of the process. The scope of a variable is limited to the process where is was declared. It cannot be accessed outside of that process. Within the process, variables behave exactly like they do in any other programming language. If you assign a value to in on one line, and read it on the next line, the variable will contain the new value.

Signals, on the other hand, will behave differently. If you assign a new value to a signal on one line of code, and read it on the next line, you will read the old value! It will seem like the assignment has been ignored.

This is because of how VHDL simulators work. VHDL is an event driven language, and VHDL simulators are event schedulers that work with time-steps. When you assign a new value to a signal, the simulator notes that at the next time-step, the signal will get that value.

The next question is of course, how to produce a time-step? By using Wait statements is the answer. All processes must contain one form of Wait statement (or sensitivity list). The new value which we assigned to the signal will become effective only when the process hits the Wait statement. If and when the process wakes up again, it will be at a future time-step, and the signal will have its new value.

What will happen if we try to assign to a signal several times before the program hits a Wait statement? The signal will get the last value that we assign to it. Remember, when you assign to a signal, the simulator schedules that value onto the signal at the next time-step. If we assign twice to a signal within the same time-step, we overwrite that future value. The result is that the signal will get the last assigned value, and all the other ones will be forgotten.

This behavior is often exploited by VHDL developers. You can assign a "default" value to a signal, and overwrite it later within the same process. We will do that in a video later in this tutorial series.