Скачать или смотреть SystemVerilog Unit Testing (SVUnit) -- Verilog Module Example

We introduce a SystemVerilog unit testing framework from AgileSoC called SVUnit. We show how to create example SVUnit tests to test a Verilog module.

Example from the video: http://www.edaplayground.com/s/exampl...

SVUnit is a lightweight framework capable of testing Verilog modules, SystemVerilog classes, methods, interfaces, and much more.

For more information on SVUnit, go to: http://www.agilesoc.com/svunit/

Recommend viewing in 720p quality or higher.

About EDA Playground:

EDA Playground is a web browser-based integrated development environment (IDE) for simulation of SystemVerilog, Verilog, VHDL, and other HDLs. EDA Playground is a free web application that allows users to edit, simulate, share, synthesize, and view waves for hardware description language (HDL) code. It is the first online HDL development environment and waveform viewer for the semiconductor industry.

EDA Playground homepage: http://www.edaplayground.com

Engineers have used EDA Playground for:
-- creating hands-on training for students
-- demonstrating best practices to other engineers
-- asking SystemVerilog questions on StackOverflow and other online forums
-- testing candidates' coding skills during technical interviews (phone and in-person)
-- quick prototyping -- trying something before inserting the code into a large code base
-- checking whether their RTL syntax/code is synthesizable

EDA Playground is actively seeking partners to integrate additional EDA tools. Future tools will include formal verification, linting, and analog and mixed-signal support.