Скачать или смотреть MiniFloat-NN: A RISC-V ISA Extension for Low-Precision NN Training - Luca Bertaccini, ETH Zürich

MiniFloat-NN: A RISC-V ISA Extension for Low-Precision NN Training - Luca Bertaccini, ETH Zürich

With neural network (NN) models getting exponentially larger, algorithmic and architectural advancements are necessary to face the new memory and compute requirements efficiently. In this context, low-precision floating-point (FP) formats play a key role as they reduce the memory footprint of NN models and open opportunities to boost the efficiency of training-oriented architectures. Such benefits drew the attention of the RISC-V community, which plans to explore new FP formats in the proposed FP SIG. We present MiniFloat-NN, a RISC-V instruction set architecture extension for low-precision NN training supporting two 16-bit and two 8-bit FP formats. The extension is based on widening sum-of-dot-products instructions and three-term additions. Such instructions are carried out on a dedicated hardware module that we integrate into an open-source FP unit. Finally, we enhance an open-source RISC-V compute cluster, which can be hierarchically replicated to build large manycore systems, with MiniFloat-NN capabilities, enabling up to a 7.2x efficiency increase with respect to the baseline system working on FP64. Our work shows the benefits of proposed lines of work for the RISC-V FP SIG.