Скачать или смотреть VHDL UDP protocol stack AXI Ethernet DMA transmission SFP output

This design calls Xilinx's AXI 1G/2.5G Ethernet Subsystem IP and implements the MAC layer design of UDP communication using a UDP protocol stack written in hardware language. The AXI 1G/2.5G Ethernet Subsystem IP core of Xilinx is called to implement the function of a network transformer, thus realizing the solution of UDP communication without external network chips; The UDP protocol stack has been encapsulated as a FIFO interface, allowing users to operate UDP transmission and reception without worrying about complex UDP protocols, but only about simple user interface timing, which is very simple; This design calls AXI DMA and MicroBlaze to enable the soft core to initiate UDP communication through DMA. MicroBlaze can also be replaced by zynq, realizing the function of PS software in zynq to achieve 1G Gigabit network UDP communication by calling PL hardware resources;
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