Скачать или смотреть MiM: Specification-Driven Verification for Analog and Mixed-Signal Chip Verification

by Henry Chang and Ken Kundert

We describe our specification-driven approach to analog and mixed-signal chip level verification. We use MiM to generate Verilog-AMS and SystemVerilog models for the analog blocks, and use MiM to generate a self checking testbench that compares the model to the schematic to confirm that the model is functionally equivalent to the schematic, and that the schematic functionally matches the specifications.

Most analog verification efforts either fail or are ineffective because it is too time consuming to generate high quality models and testbenches for all the blocks that need to be created to enable a complete analog system-level verification. Even if models are created, comprehensive self-checking testbenches are rare. Instead, the validation of the models is often pushed on to the designers, which results in delays, incomplete validation, and unhappy designers.

With MiM a simple spec sheet is created that describes the functional aspects of each block that can easily be understood by the designer and the verification engineer. MiM generates a high-quality functional model and comprehensive self-checking testbench from this spec sheet at the push of a button. The testbench compares the results from the model against those from the schematic and highlights any meaningful differences. MiM produces high-quality functional models and testbenches that employ the best known modeling and verification practices. The result is a complete set of AMS models in which you have high confidence and which you produced in a reasonable amount of time for a reasonable price.

MiM gives you the productivity to create and validate all your models.

For more information on MiM, please contact [email protected]
For more information on Designer's Guide, please visit www.designers-guide.com
The playlist for all of our videos on our specification-driven approach can be found at:    • Specification-Driven Verification and MiM  

Please view the video in 1080p60 for the clearest image.

Ken Kundert and Henry Chang founded Designer’s Guide in 2005. Since the company's founding they’ve been assisting semiconductor companies with analog, mixed-signal and chip verification. They started with consulting. Then as they gained insight into the issues and problems and solutions, they began teaching classes. It was then, after seeing many projects and talking to many people, that they realized where the true bottleneck is for analog and mixed-signal verification. They then developed a software tool that removes this bottleneck and makes it so that one doesn’t have to be an expert to have good models and to verify that one’s models and schematics are equivalent. The tool is called MiM, which stands for Models in Minutes. MiM does a lot more though, and that’s what they’ll be discussing on this YouTube Channel. Designer's Guide also provides on shore and off shore analog, mixed-signal, chip-level modeling and verification services.

Ken Kundert was a fellow at Cadence prior to founding Designer’s Guide. He invented the Spectre simulator, leading its development and leading the related efforts of creating the Verilog-A and Verilog-AMS languages as well as developing Cadence’s AMS Designer mixed-signals simulator. Prior to that Ken received his Ph.D. in Electrical Engineering and Computer Science from UC Berkeley and had been an analog and microwave designer prior working at HP and Tektronix.

Henry Chang was an architect at Cadence prior to founding Designer’s Guide. He worked in R&D and methodology services where he worked on analog and mixed-signal design flows — focused on improving the efficiency of design and on verification. Prior to Cadence, Henry also received his Ph.D. from UC Berkeley where his research was focused a top-down design driven methodology
for analog circuits.

Both have authored many patents, journal articles, research papers, and books.