Скачать или смотреть First machine learning protection against side-channel attacks for post-silicon security patch

The first side-channel attack counteraction via machine learning for post-silicon HW security patching is here presented. This is another scientific/technical advance from the Green IC group led by Prof. Massimo Alioto, insights into our research and its impact in the world.

In this work, machine learning-based side-channel attack counteraction is presented for security upgradeability via retraining, upon vulnerability discovery after deployment. Based on stdcell design, direct compensation of information-leaking power contributions reduces the power overhead over conventional indiscriminate compensation of total power fluctuations. A 40nm chip demonstrates design reuse across crypto algorithms, patching against a new attack to PRESENT, and AES protection under more than 1.2B traces.

In this work, a design-adaptive counteraction approach against side-channel attacks is introduced to enable post-silicon upgrade-ability and security fixes over time (“hardware patch”), reuse across ciphers under single- and multi-standard encryption, and targeted compensation of information-sensitive power contributions for low power overhead. The latter are actively compensated by a lightweight machine learning power model and a power compensator, whose weight updates allow post-silicon improvements and large-scale deployment of security fixes throughout the device lifespan. A 40nm testchip demonstrates adaptability across ciphers and their implementations, while retaining conventional standard cell-based design for easy adoption, system integration and in-situ protection. Hardware patching of new vulnerabilities is demonstrated by introducing and then counteracting a newly proposed attack to PRESENT via weight update.

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