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VLSI POINT has completed it's 1 year successfully. On this special occasion we have launched our website. Visit our website and get verilog hand written notes, verilog interview questions, verilog practice questions, lecture slides etc.

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Don't miss the Verilog videos-

Verilog Complete Tutorial in English:

Introduction to HDL | What is HDL? | #1 | Verilog in English
   • Introduction to HDL | What is HDL? | #1 | ...  

Level of abstraction in Verilog | #2 | Verilog in English
   • Level of abstraction in Verilog | #2 | Ver...  

Modules and Instantiation in Verilog | #3 | Verilog in English
   • Modules and Instantiation in Verilog | #3 ...  

Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in English
   • Simulation, Synthesis and Design methodolo...  

Data types in Verilog | #5 | Introduction | Verilog in English | VLSI Point
   • Data types in Verilog | #5 | Introduction ...  

Net Data type in Verilog | #6 | Verilog in English | VLSI Point
   • Net Data type in Verilog | #6 | Verilog in...  

Reg Datatype in Verilog | # 7 | Verilog in English | VLSI Point
   • Reg Datatype in Verilog | # 7 | Verilog in...  

Vectors, Arrays, Memories, Parameters, Strings in Verilog | #8 | verilog in English | VLSI Point
   • Vectors, Arrays, Memories, Parameters, Str...  

Operators in Verilog | #9 | Verilog in English | VLSI Point
   • Operators In Verilog | #9 | Verilog in Eng...  

Practice-Set | #10 | Verilog in English | VLSI Point
   • Practice-Set | #10 | Verilog in English | ...  

Gate Level Modeling | #11 | Verilog in English | VLSI Point
   • Gate Level Modeling  | #11 | Verilog in En...  

Dataflow Modeling | #12 | Verilog in English | VLSI Point
   • Dataflow Modeling | #12 | Verilog in Engli...  

Behavioral Modeling | #13 | Verilog in English | VLSI Point
   • Behavioral Modeling | #13  | Verilog in En...  

Compiler directive & System tasks in Verilog | #14 | Verilog in English
   • Compiler directive & System tasks in Veril...  

Task and Functions in Verilog | #15 | Verilog in English
   • Task and Functions in Verilog | #15 |  Ver...  

Test Bench writing in Verilog | #16 | Verilog in English | VLSI POINT
   • Test Bench writing in Verilog  | #16 | Ver...  

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Verilog Complete Tutorial in Hindi:

Introduction to HDL | What is HDL? | #1 | Verilog in Hindi
   • Introduction to HDL | What is HDL? | #1 | ...  

Level of abstraction in Verilog | #2 | Verilog in Hindi
   • Level of abstraction in Verilog | #2 | Ver...  

Modules and Instantiation in Verilog | #3 | Verilog in Hindi
   • Modules and Instantiation in Verilog | #3 ...  

Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in Hindi
   • Simulation, Synthesis and Design methodolo...  

Data types in Verilog | #5 | Introduction | Verilog in Hindi | VLSI Point
   • Data types in Verilog | #5 | Introduction ...  

Net Data type in Verilog | #6 | Verilog in Hindi | VLSI Point
   • Net Data type in Verilog | #6 | Verilog in...  

Reg Datatype in Verilog | # 7 | Verilog in Hindi | VLSI Point
   • Reg Datatype in Verilog | # 7 | Verilog in...  

Vectors, Arrays, Memories, Parameters, Strings in Verilog | #8 | verilog in Hindi | VLSI Point
   • Vectors, Arrays, Memories, Parameters, Str...  

Operators in Verilog | #9 | Verilog in Hindi | VLSI Point
   • Operators in Verilog | #9 | Verilog in Hin...  

Practice-Set | #10 | Verilog in Hindi | VLSI Point
   • Practice-Set | #10 | Verilog in Hindi | VL...  

Gate Level Modeling | #11 | Verilog in Hindi | VLSI Point
   • Gate Level Modeling  | #11 | Verilog in Hi...  

Dataflow Modeling | #12 | Verilog in Hindi | VLSI Point
   • Dataflow Modeling | #12 | Verilog in Hindi...  

Behavioral Modeling | #13 | Verilog in Hindi | VLSI Point
   • Behavioral Modeling | #13  | Verilog in Hi...  

Compiler directive & System tasks in Verilog | #14 | Verilog in Hindi
   • Compiler directive & System tasks in Veril...  

Task and Functions in Verilog | #15 | Verilog in Hindi
   • Task and Functions in Verilog | #15 |  Ver...  discussed

Test Bench writing in Verilog | #16 | Verilog in Hindi | VLSI POINT
   • Test Bench writing in Verilog  | #16 | Ver...  

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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar