Скачать или смотреть Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability

Abstract—Error correction code (ECC) and built-in selfrepair
(BISR) techniques by using redundancies have been
widely used for improving the yield and reliability of embedded
memories. The target faults of these two schemes are soft errors
and permanent (hard) faults, respectively. In recent works, there
are also some techniques integrating ECC and BISR to deal with
soft errors and hard defects simultaneously. However, this will
compromise reliability, since some of the ECC protection capability
is used for repairing single hard faults. To cure this dilemma,
we propose an ECC-enhanced BISR (EBISR) technique, which
uses ECC to repair single permanent faults first and spares
for the remaining faults in the production/power-ON test and
repair stage. However, techniques are proposed to maintain the
original reliability during the online test and repair stage. We also
propose the corresponding hardware architecture for the EBISR
scheme. A simulator is implemented to evaluate the hardware
overhead (HO), repair rate, reliability, and performance penalty.
Experimental results show that the proposed EBISR scheme can
improve yield and reliability significantly with negligible HO and
performance penalty.

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