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#Peripheral_Component_Interconnect
PCI configuration space is the underlying way that the Conventional PCI, PCI-X and PCI Express perform auto configuration of the cards inserted into their bus.
PCI devices have a set of registers referred to as configuration space and PCI Express introduces extended configuration space for devices.
Configuration space registers are mapped to memory locations.
Device drivers and diagnostic software must have access to the configuration space, and operating systems typically use APIs to allow access to device configuration space.
When the operating system does not have access methods defined or APIs for memory mapped configuration space requests, the driver or diagnostic
software has the burden to access the configuration space in a manner that is compatible with the operating system's underlying access rules.
In all systems, device drivers are encouraged to use APIs provided by the operating system to access the configuration space of the device.
One of the major improvements the PCI Local Bus had over other I/O architectures was its configuration mechanism.
In addition to the normal memory-mapped and I/O port spaces, each device function on the bus has a configuration space, which is 256 bytes long, addressable by knowing the eight-bit PCI bus,
five-bit device, and three-bit function numbers for the device （commonly referred to as the BDF or B/D/F, as abbreviated from bus/device/function）.
This allows up to 256 buses, each with up to 32 devices, each supporting eight functions.
A single PCI expansion card can respond as a device and must implement at least function number zero.
The first 64 bytes of configuration space are standardized; the remainder are available for vendor-defined purposes.
In order to allow more parts of configuration space to be standardized without conflicting with existing uses, there can be a list of capabilitie...