RISC-V Logisim Immediate Generator

Learn about the RISC-V instruction set architecture by building hardware. In this video, I use Logisim to build the Immediate Generator that will eventually be incorporated into an RV32I CPU that can be synthesized on to an FPGA.

Immediates touch on many classes of instructions and are fundamental to understanding the RISC-V philosophy.

There are a number of resources that I recommend you study as you go on this journey with me:

RISC-V Reference Card: https://www.cl.cam.ac.uk/teaching/161...
Design of the RISC-V Instruction Set Architecture: https://digitalassets.lib.berkeley.ed...
Great Ideas in Computer Architecture (week 2 and 4): https://inst.eecs.berkeley.edu/~cs61c...
RISC-V Specification: https://riscv.org/wp-content/uploads/...

Other helpful resources:

Online RISC-V assembler: https://riscvasm.lucasteske.dev
Logisim Evolution: https://github.com/logisim-evolution/...