RiscV Logisim Load Datapath

Learn about the RISC-V instruction set architecture by building hardware. In this video, I add load instructions to the datapath in order to load bytes, half words, and words into the register file.

I highly recommend you watch the videos on this playlist to this point as I use many of the modules built to date:

   • RISC-V Logisim Program Counter  

There are a number of resources that I recommend you study as you go on this journey with me:

Github for Python Source: https://github.com/chuckb/rv32icltrom...
RISC-V Reference Card: https://www.cs.sfu.ca/~ashriram/Cours...
Design of the RISC-V Instruction Set Architecture: https://digitalassets.lib.berkeley.ed...
Great Ideas in Computer Architecture (week 2 and 4): https://inst.eecs.berkeley.edu/~cs61c...
RISC-V Specification: https://riscv.org/wp-content/uploads/...
Truth Table: https://docs.google.com/spreadsheets/...

Other helpful resources:

Online RISC-V assembler: https://riscvasm.lucasteske.dev
Logisim Evolution: https://github.com/logisim-evolution/...