Скачать или смотреть 2018 EuroLLVM Developers’ Meeting: G. Chatelet “Measuring x86 instruction latencies with LLVM ”

http://llvm.org/devmtg/2018-04/
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Measuring x86 instruction latencies with LLVM - Guillaume Chatelet, Google

Slides: http://llvm.org/devmtg/2018-04/slides...
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Instruction latencies are at the core of the instruction scheduling process of the LLVM backend. This information is usually provided by CPU vendors in the form of reference manuals or as direct contributions to the LLVM code base. Validating and correcting this information is hard. Dr. Agner Fog has been maintaining a database of latencies and decompositions for several years; his approach is to carefully craft pieces of assembly and use PMUs (Performance Monitoring Units).

We present a tool based on LLVM and inspired by Fog that automates the process of measuring instruction latencies and infers the assignment of micro-operations to ports. Our goal is to feed this information back into LLVM configuration files.
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